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MC74HC589A 8-Bit Serial or Parallel-Input/Serial-Output Shift Register with 3-State Output
High-Performance Silicon-Gate CMOS
The MC74HC589A device consists of an 8-bit storage latch which feeds parallel data to an 8-bit shift register. Data can also be loaded serially (see the Function Table). The shift register output, QH, is a 3-state output, allowing this device to be used in bus-oriented systems. The HC589A directly interfaces with the SPI serial data port on CMOS MPUs and MCUs.
Features http://onsemi.com MARKING DIAGRAMS
16
16 1
PDIP-16 N SUFFIX CASE 648 1
MC74HC589AN AWLYYWW
16
16 1
* * * * * * * *
Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 526 FETs or 131.5 Equivalent Gates Pb-Free Packages are Available*
SOIC-16 D SUFFIX CASE 751B 1
HC589A AWLYWW
16
16 1
TSSOP-16 DT SUFFIX CASE 948F 1 16
HC 589A ALYW
16 1
SOEIAJ-16 CASE 966 1
74HC589A ALYW
A L, WL Y, YY W, WW
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
February, 2005 - Rev. 3
Publication Order Number: MC74HC589A/D
MC74HC589A
SERIAL DATA INPUT SA 14
A B PARALLEL DATA INPUTS C D E F G H LATCH CLOCK
15 1 2 3 4 5 6 7 12 9 QH SERIAL DATA OUTPUT DATA LATCH SHIFT REGISTER VCC = PIN 16 GND = PIN 8 B C D E F G H GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC A SA SERIAL SHIFT/ PARALLEL LOAD LATCH CLOCK SHIFT CLOCK OUTPUT ENABLE QH
SHIFT CLOCK
11
Figure 2. Pin Assignment
SERIAL SHIFT/ 13 PARALLEL LOAD 10 OUTPUT ENABLE
Figure 1. Logic Diagram
ORDERING INFORMATION
Device MC74HC589AN MC74HC589ANG MC74HC589AD MC74HC589ADG MC74HC589ADR2 MC74HC589ADR2G MC74HC589ADTR2 MC74HC589AFEL MC74HC589AFELG Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) TSSOP-16* SOEIAJ-16 SOEIAJ-16 (Pb-Free) Shipping 2000 / Box 2000 / Box 48 Units / Rail 48 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 2500 Tape & Reel 2000 Tape & Reel 2000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74HC589A
MAXIMUM RATINGS
Symbol VCC Vin Vout Iin Iout ICC IGND TSTG TL TJ qJA DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance PDIP SOIC TSSOP PDIP SOIC TSSOP Parameter (Referenced to GND) (Referenced to GND) (Referenced to GND) Value *0.5 to )7.0 *0.5 v VCC )0.5 *0.5 v VCC )0.5 $20 $35 $75 $75 *65 to )150 260 )150 78 112 148 750 500 450 Level 1 Oxygen Index: 30% - 35% Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Above VCC and Below GND at 85_C (Note 4) UL 94 V-0 @ 0.125 in u4000 u200 u1000 $300 V Unit V V V mA mA mA mA _C _C _C _C/W
PD
Power Dissipation in Still Air at 85_C
mW
MSL FR VESD
Moisture Sensitivity Flammability Rating ESD Withstand Voltage
ILatchup
Latchup Performance
mA
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22-A114-A. 2. Tested to EIA/JESD22-A115-A. 3. Tested to JESD22-C101-A. 4. Tested to EIA/JESD78. 5. For high frequency or heavy load considerations, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
IIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII I I
VCC DC Supply Voltage (Referenced to GND) 2.0 0 6.0 V V Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) VCC Operating Temperature, All Package Types Input Rise and Fall Time (Figure 3) *55 0 0 0 )125 1000 800 500 400 _C ns tr, tf VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V 6. Unused inputs may not be left open. All inputs must be tied to a high-logic voltage level or a low-logic input voltage level.
Symbol
Parameter
Min
Max
Unit
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II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I II II I I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
7. Information on typical parametric values can be found in the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND, Note 7)
Symbol
ICC
IOZ
Iin
VOL
VOH
VIL
VIH
Maximum Quiescent Supply Current (per Package)
Maximum Three-State Leakage Current
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
Vout = 0.1 V or VCC *0.1 V |Iout| v 20 mA
Vout = 0.1 V or VCC *0.1 V |Iout| v 20 mA
Vin = VCC or GND Iout = 0 mA
Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND
Vin = VCC or GND
Vin = VIH or VIL
Vin = VIH |Iout| v 20 mA
Vin = VIH or VIL
Vin = VIH or VIL |Iout| v 20 mA
Test Conditions
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MC74HC589A
|Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA
|Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA
4 VCC 6.0 6.0 6.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 2.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 V *55_C to 25_C $0.5 $0.1 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 0.26 0.26 0.26 2.48 3.98 5.48 0.1 0.1 0.1 1.9 4.4 5.9 4 Guaranteed Limit v85_C $5.0 $1.0 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 0.33 0.33 0.33 2.34 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9 40 v125_C $1.0 $10 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 0.40 0.40 0.40 2.20 3.70 5.20 160 0.1 0.1 0.1 1.9 4.4 5.9 Unit mA mA mA V V V V
MC74HC589A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns, Notes 8 and 9)
VCC Symbol fmax Parameter Maximum Clock Frequency (50% Duty Cycle) (Figures 4 and10) V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - - Guaranteed Limit *55_C to 25_C 6.0 15 30 35 v85_C 4.8 10 24 28 v125_C 4.0 8.0 20 24 Unit MHz
II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II II I I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
tPLH, tPHL Maximum Propagation Delay, Latch Clock to QH (Figures 3 and 10) 175 100 40 30 160 90 30 25 160 90 30 25 150 80 27 23 150 80 27 23 60 23 12 10 10 15 225 110 50 40 200 130 40 30 200 130 40 30 170 100 30 25 170 100 30 25 75 27 15 13 10 15 275 125 60 50 240 160 48 40 240 160 48 40 200 130 40 30 200 130 40 30 90 31 18 15 10 15 ns tPLH, tPHL Maximum Propagation Delay, Shift Clock to QH (Figures 4 and 10) ns tPLH, tPHL Maximum Propagation Delay, Serial Shift/Parallel Load to QH (Figures 6 and 10) ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to QH (Figures 5 and 11) ns tPZL, tPZH Maximum Propagation Delay, Output Enable to QH (Figures 5 and 11) ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 3 and 10) ns Cin Maximum Input Capacitance pF pF Cout Maximum Three-State Output Capacitance (Output in High-Impedance State) 8. For propagation delays with loads other than 50 pF, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D). 9. Information on typical parametric values can be found in the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25_C, VCC = 5.0 V 50 CPD Power Dissipation Capacitance (per Package)* pF *Used to determine the no-load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II II I I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
10. Information on typical parametric values can be found in the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (Input tr = tf = 6 ns, Note 10)
Symbol
tr, tf
tw
tw
tw
th
th
tsu
tsu
tsu
Minimum Setup Time, Serial Data Input SA to Shift Clock (Figure 8)
Minimum Setup Time, Serial Shift/Parallel Load to Shift Clock (Figure 9)
Maximum Input Rise and Fall Times (Figure 3)
Minimum Pulse Width, Serial Shift/Parallel Load (Figure 6)
Minimum Pulse Width, Latch Clock (Figure 3)
Minimum Pulse Width, Shift Clock (Figure 4)
Minimum Hold Time, Shift Clock to Serial Data Input SA (Figure 8)
Minimum Hold Time, Latch Clock to A-H (Figure 7)
Minimum Setup Time, A-H to Latch Clock (Figure 7)
Parameter
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MC74HC589A
6 VCC 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 V *55_C to 25_C 1000 800 500 400 100 40 20 17 100 40 20 17 100 40 20 17 80 40 16 14 80 40 16 14 75 40 15 13 25 10 5 5 5 5 5 5 Guaranteed Limit v85_C 1000 800 500 400 100 50 20 17 100 50 20 17 125 50 25 21 125 50 25 21 125 50 25 21 95 50 19 16 30 12 6 6 5 5 5 5 v125_C 1000 800 500 400 120 60 24 20 120 60 24 20 150 60 30 26 150 60 30 26 150 60 30 26 110 60 23 19 40 15 8 7 5 5 5 5 Unit ns ns ns ns ns ns ns ns ns
MC74HC589A
FUNCTION TABLE
Inputs Output Enable H L L L L L L Serial Shift/ Parallel Load X H L H L H H X L, H, L, H, Latch Clock X Shift Clock X L, H, X L, H, X Serial Input SA X X X X X D D Parallel Inputs A-H X a-h X X a-h X a-h Data Latch Contents X a-h U U a-h Resulting Function Shift Register Contents X U LRN SRN U a-h SRA = D, SRN SRN+1 SRA = D, SRN SRN+1 Output QH Z U LRH U h SRG SRH SRG SRH
Operation Force Output into High Impedance State Load Parallel Data into Data Latch Transfer Latch Contents to Shift Register Contents of Input Latch and Shift Register are Unchanged Load Parallel Data into Data Latch and Shift Register Shift Serial Data into Shift Register Load Parallel Data in Data Latch and Shift Serial Data into Shift Register LR SR a-h D = = = =
*
a-h
latch register contents shift register contents data at parallel data inputs A-H data (L, H) at serial data input SA
U = remains unchanged X = don't care Z = high impedance * = depends on Latch Clock input
Switching Waveforms
tr LATCH CLOCK 90% 50% 10% tw tPLH QH 90% 50% 10% tTLH tTHL tPHL tPLH QH 50% tPHL tf VCC GND SHIFT CLOCK 50% GND tw
1/fmax VCC
Figure 3. (Serial Shift/Parallel Load = L)
Figure 4. (Serial Shift/Parallel Load = H)
OUTPUT ENABLE
VCC 50% GND tPZL tPLZ HIGH IMPEDANCE 10% 90% VOL VOH HIGH IMPEDANCE QH SERIAL SHIFT/ PARALLEL LOAD tw 50% tPLH 50% 50% GND tPHL VCC
QH
50% tPZH tPHZ
QH
50%
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Figure 6.
MC74HC589A
Switching Waveforms
DATA VALID A-H 50% GND tsu LATCH CLOCK th 50% SHIFT CLOCK tsu th 50% VCC SA DATA VALID 50% GND VCC
Figure 7.
Figure 8.
VCC SERIAL SHIFT/ PARALLEL LOAD SHIFT CLOCK 50% GND tsu 50%
Figure 9.
TEST POINT OUTPUT DEVICE UNDER TEST CL * DEVICE UNDER TEST TEST POINT OUTPUT 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 10. Test Circuit
Figure 11. Test Circuit
Pin Descriptions Data Inputs
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
data in stage H is shifted out QH, being replaced by the data previously stored in stage G.
Latch Clock (Pin 12)
Parallel data inputs. Data on these inputs are stored in the data latch on the rising edge of the Latch Clock input.
SA (Pin 14)
Data latch clock. A low-to-high transition on this input loads the parallel data on inputs A-H into the data latch.
Output Enable (Pin 10)
Serial data input. Data on this input is shifted into the shift register on the rising edge of the Shift Clock input if Serial Shift/Parallel Load is high. Data on this input is ignored when Serial Shift/Parallel Load is low. Control Inputs
Serial Shift/Parallel Load (Pin 13)
Active-low output enable A high level applied to this pin forces the QH output into the high impedance state. A low level enables the output. This control does not affect the state of the input latch or the shift register. Output
QH (Pin 9)
Shift register mode control. When a high level is applied to this pin, the shift register is allowed to serially shift data. When a low level is applied to this pin, the shift register accepts parallel data from the data latch.
Shift Clock (Pin 11)
Serial data output. This pin is the output from the last stage of the shift register. This is a 3-state output.
Serial shift clock. A low-to-high transition on this input shifts data on the serial data input into the shift register and
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MC74HC589A
SHIFT CLOCK SERIAL DATA INPUT, SA OUTPUT ENABLE SERIAL SHIFT/ PARALLEL LOAD LATCH CLOCK A B L L H L L L L L
C D
L L
H L
L L
L L
PARALLEL DATA INPUTS
E
L
H
L
H
F G
L L
H L
L L
H L
H
L
H H L H H L H
H L L H L L L
H L
QH
HIGH IMPEDANCE
H
H
HH
LOAD RESET LATCH LATCH AND SHIFT REGISTER
EEEE
SERIAL SHIFT
SERIAL SHIFT
SERIAL SHIFT
SERIAL SHIFT
PARALLEL LOAD SHIFT REGISTER
LOAD LATCH
PARALLEL LOAD SHIFT REGISTER
PARALLEL LOAD, LATCH, AND SHIFT REGISTER
Figure 12. Timing Diagram
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MC74HC589A
OUTPUT 10 ENABLE 14 SA SHIFT 11 CLOCK SERIAL SHIFT/ 13 PARALLEL LOAD 12 LATCH CLOCK 15 A
STAGE A D Q C
S D CQ R
STAGE B B 1 D Q C
S D CQ R
PARALLEL DATA INPUTS
C
2
STAGE C*
D
3
STAGE D*
E
4
STAGE E*
F
5
STAGE F*
G
6
STAGE G* STAGE H VCC S D CQ R
H
7
D Q C
9
QH
*Stages C thru G (not shown in detail) are identical to stages A and B above.
Figure 13. Logic Detail
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MC74HC589A
PACKAGE DIMENSIONS
PDIP-16 N SUFFIX CASE 648-08 ISSUE T
-A-
16 9
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC74HC589A
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE A
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE N-N DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC -W- M 0_ 8_ 0_ 8_
H D G
DETAIL E
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CCC EE CCC EE
MC74HC589A
PACKAGE DIMENSIONS
SOEIAJ-16 CASE 966-01 ISSUE O
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74HC589A
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MC74HC589A/D

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